Kaohsiung, Taiwan

Jung Fu Lee

This inventor holds 1 USPTO granted patent. Top assignee: Winway Technology Co., Ltd.. Active years: 2014.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Jung Fu Lee. Retrieved from https://idiyas.com/inventor/jung-fu-lee

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


% Patents Active = 100.0

Average Co-Inventor Count = 3.0

ph-index = 1

Forward Citations = 2(Granted Patents)


Company Filing History:


Years Active: 2014

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1 patent (USPTO):Explore Patents

Title: Innovations of Jung Fu Lee in Wafer Probe Card Technology

Introduction

Jung Fu Lee is a notable inventor based in Kaohsiung, Taiwan. He has made significant contributions to the field of semiconductor testing through his innovative designs. His work primarily focuses on improving the efficiency and operational speed of wafer probe cards.

Latest Patents

Jung Fu Lee holds a patent for a wafer probe card, which features an adapter module and a probe module that can be detachably mounted together. The design includes a holding member and an interposer within the adapter module, while the probe module consists of a frame assembly, a space transformer, and a probe assembly. This modular approach allows for easy replacement of faulty elements without the need to detach all components, thereby enhancing operational efficiency.

Career Highlights

Jung Fu Lee is currently employed at Winway Technology Co., Ltd., where he continues to develop innovative solutions in semiconductor technology. His patent demonstrates his commitment to advancing the industry and improving testing methodologies.

Collaborations

Some of his coworkers include Chia-Huang Wang and Hsin Chieh Lu, who contribute to the collaborative environment at Winway Technology Co., Ltd. Their teamwork fosters innovation and drives the development of cutting-edge technologies.

Conclusion

Jung Fu Lee's contributions to wafer probe card technology exemplify his innovative spirit and dedication to enhancing semiconductor testing processes. His work not only improves efficiency but also sets a standard for future developments in the field.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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