Hsinchu, Taiwan

Juing-Yi Cheng

This inventor holds 1 USPTO granted patent. Top assignee: National Science Council. Active years: 1999.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Juing-Yi Cheng. Retrieved from https://idiyas.com/inventor/juing-yi-cheng-tlnezi6t

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

% Patents Active = 100.0

Average Co-Inventor Count = 4.0

ph-index = 1

Forward Citations = 60(Granted Patents)


Company Filing History:


Years Active: 1999

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1 patent (USPTO):Explore Patents

Title: Juing-Yi Cheng and Low-Temperature Thin-Film Transistor Fabrication.

Introduction

Juing-Yi Cheng is an inventor associated with Hsinchu, Taiwan, and the National Science Council. His work includes a method for fabricating polycrystalline silicon and silicon-germanium thin-film transistors at low temperatures and with a low thermal budget.

Latest Patents

The available information lists 1 patent for Cheng: “Method to Fabricate the Thin Film Transistor.” The invention combines ultrahigh-vacuum chemical vapor deposition (UHV/CVD) with chemical mechanical polishing (CMP). UHV/CVD enables poly-Si and poly-Si₁₋ₓGeₓ films to be deposited without an annealing step, while an ultraclean growth environment and low base pressure help reduce defects. CMP improves the films’ surface morphology, supporting the fabrication of high-performance top-gate thin-film transistors.

Career Highlights

Cheng’s listed patent focuses on addressing a key fabrication challenge: improving the surface quality of deposited polycrystalline films so they can be used effectively in top-gate transistor structures. The method aims to achieve this while limiting processing temperature and thermal exposure.

Collaborations

Cheng’s listed coworkers include Hsiao-Yi Lin and Chun-Yen Chang. The available information associates his work with the National Science Council.

Conclusion

Juing-Yi Cheng’s patent describes a low-temperature approach to thin-film transistor fabrication that pairs UHV/CVD deposition with CMP surface improvement.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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