This inventor holds 1 USPTO granted patent and 1 published patent application. Top assignee: Industrial Technology Research Institute. Active years: 2011.
Company Filing History:
Years Active: 2011
Title: Jui-Ching Hsieh: Innovator in Chip Package Technology
Introduction
Jui-Ching Hsieh is a notable inventor based in Taichung, Taiwan. She has made significant contributions to the field of chip packaging technology. Her innovative work has led to the development of a unique chip package structure that enhances heat dissipation.
Latest Patents
Jui-Ching Hsieh holds a patent for a "Chip package structure and method of fabricating the same." This patent describes a chip package structure that includes a heat dissipation substrate, a chip, and a heterojunction heat conduction buffer layer. The chip is positioned on the heat dissipation substrate, while the heterojunction heat conduction buffer layer is situated between the heat dissipation substrate and the chip. This buffer layer consists of multiple pillars that are perpendicular to the heat dissipation substrate, with an aspect ratio of each pillar ranging from about 3:1 to 50:1. She has 1 patent to her name.
Career Highlights
Jui-Ching Hsieh is affiliated with the Industrial Technology Research Institute, where she continues to advance her research and development efforts. Her work is pivotal in improving the efficiency and performance of chip packaging solutions.
Collaborations
Some of her notable coworkers include Yu-Jen Wang and Chin-Horng Wang, who contribute to her innovative projects and research initiatives.
Conclusion
Jui-Ching Hsieh's contributions to chip packaging technology exemplify her dedication to innovation and research. Her patented work is a testament to her expertise and impact in the field.