The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 02, 2011

Filed:

May. 26, 2009
Applicants:

Jui-ching Hsieh, Taichung, TW;

Pin Chang, Hsinchu, TW;

Chung-de Chen, Miaoli County, TW;

Li-chi Pan, Hsinchu, TW;

Yu-jen Wang, Taipei County, TW;

Chin-horng Wang, Hsinchu, TW;

Inventors:

Jui-Ching Hsieh, Taichung, TW;

Pin Chang, Hsinchu, TW;

Chung-De Chen, Miaoli County, TW;

Li-Chi Pan, Hsinchu, TW;

Yu-Jen Wang, Taipei County, TW;

Chin-Horng Wang, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

A chip package structure including a heat dissipation substrate, a chip and a heterojunction heat conduction buffer layer is provided. The chip is disposed on the heat dissipation substrate. The heterojunction heat conduction buffer layer is disposed between the heat dissipation substrate and the chip. The heterojunction heat conduction buffer layer includes a plurality of pillars perpendicular to the heat dissipation substrate. The aspect ratio of each pillar is between about 3:1 and 50:1.


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