Austin, TX, United States of America

Joseph Roland Verock

This inventor holds 2 USPTO granted patents. Top assignee: International Business Machines Corporation. Active years: 2003.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Joseph Roland Verock. Retrieved from https://idiyas.com/inventor/joseph-roland-verock

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


% Patents Active = 100.0

Average Co-Inventor Count = 2.7

ph-index = 1

Forward Citations = 4(Granted Patents)


Company Filing History:


Years Active: 2003

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2 patents (USPTO):Explore Patents

Title: The Innovations of Joseph Roland Verock

Introduction

Joseph Roland Verock is a notable inventor based in Austin, TX, who has made significant contributions to the field of integrated circuit design. With a total of two patents to his name, Verock's work focuses on enhancing the efficiency of logical-to-physical checking processes in chip design.

Latest Patents

Verock's latest patents include an invention that allows for multiple layouts for a schematic in hierarchical logical-to-physical checking on chips. This innovation introduces an EQUATE property into the layout cell data for a layout design, enabling the identification of the schematic corresponding to the layout design. Instead of requiring the layout cell to be exploded for flat checking, the layout cell instances can be checked hierarchically. This method allows for one instance to be checked internally for compliance with design rules while the remaining instances are verified for proper connections to neighboring cells. Consequently, new layout cell designs can be created as needed without the necessity of rerunning schematic checking tools.

Another significant patent by Verock allows for hierarchical logical-to-physical checking on chips. In this invention, layout cells that share the same name as their corresponding schematic are checked hierarchically. A single instance of a specific layout cell is checked internally for compliance, while other instances are merely checked for proper connections. Layout cells that do not match any schematic name are automatically exploded for flat checking at the transistor level. This approach preserves hierarchical checking for the majority of layout cell instances, while also accommodating special layout requirements for a smaller number of cases.

Career Highlights

Verock is currently employed at International Business Machines Corporation, commonly known as IBM. His work at IBM has allowed him to contribute to advancements in chip design and integrated circuit technology.

Collaborations

Throughout his career, Verock has collaborated with notable colleagues, including Stephen Larry Runyon and Robert T Sayah. These collaborations have further enriched his contributions to the field.

Conclusion

Joseph Roland Verock's innovative patents and contributions to integrated circuit design demonstrate his expertise and commitment to advancing technology. His work continues to influence the efficiency of logical-to-physical checking processes in chip design.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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