The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 20, 2003
Filed:
Feb. 28, 2000
Stephen Larry Runyon, Pflugerville, TX (US);
Joseph Roland Verock, Austin, TX (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
Layout cells having the same name as a corresponding schematic are checked hierarchically, with a single instance of a particular layout cell being checked internally for compliance with design rules and the like while remaining instances are merely checked for proper connection to neighboring cells. Layout cells which are not named the same as any schematic are automatically exploded for flat checking at the transistor level. Thus hierarchical checking is preserved for those layout cell instances named for the corresponding schematic, which should be the large majority of cell instances in any given integrated circuit, while cell instances meeting special layout requirements, which should be a small number of cases, are supported for any given schematic.