Joseph Micahel Swenton

Title: Joseph Michael Swenton: Innovator in Integrated Circuit Testing

Introduction

Joseph Michael Swenton is a notable inventor based in Owego, NY (US). He has made significant contributions to the field of integrated circuit (IC) testing. His innovative work has led to the development of a unique patent that enhances the testing process for IC chips.

Latest Patents

Joseph Michael Swenton holds a patent for "SDD ATPG using fault rules files, SDF and node slack for testing an IC chip." This patent describes an integrated circuit test engine that extracts input to output propagation delay for each cell instance of various cell types in an IC design from an SDF file. The engine also extracts node slack for each cell instance and generates cell-aware test patterns to test fabricated IC chips for defects. These patterns are designed to sensitize and propagate transitions along the longest possible path, effectively testing for small delay defects in the chip.

Career Highlights

Joseph is currently employed at Cadence Design Systems, Inc., where he continues to innovate in the field of IC design and testing. His work is crucial in ensuring the reliability and performance of integrated circuits in various applications.

Collaborations

Throughout his career, Joseph has collaborated with talented professionals, including Arvind Chokhani and Santosh Subhaschandra Malagi. These collaborations have further enriched his contributions to the field.

Conclusion

Joseph Michael Swenton's work in integrated circuit testing exemplifies the importance of innovation in technology. His patent and career achievements highlight his role as a key figure in advancing IC testing methodologies.