Suwon, South Korea

Jooseong Yun

This inventor holds 1 USPTO granted patent. Top assignee: Samsung Electronics Ltd.. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Jooseong Yun. Retrieved from https://idiyas.com/inventor/jooseong-yun

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


Average Co-Inventor Count = 1.0

ph-index = 1


Company Filing History:


Years Active: 2026

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1 patent (USPTO):Explore Patents

Title: Jooseong Yun - Innovator in Semiconductor Technology

Introduction

Jooseong Yun is an inventor based in Suwon-si, South Korea. He is known for his contributions to semiconductor technology, particularly in the design of gate structures within semiconductor devices. Although he currently holds no granted patents, his innovative ideas are reflected in his patent applications.

Latest Patent Applications

One of Jooseong Yun's notable patent applications is titled "SEMICONDUCTOR DEVICE INCLUDING GATE STRUCTURE." This application describes a semiconductor device that features an active region and an isolation region adjacent to it. The device includes a gate trench with two portions: a first trench portion that crosses the active region and a second trench portion located in the isolation region. The design incorporates a first gate portion within the first trench and a second gate portion within the second trench. Each gate portion consists of a gate dielectric layer and a gate electrode that partially fills the gate trench. The upper surface of the gate electrode is positioned lower than the upper end of the active region, and an insulative capping pattern is placed on top of the gate electrode. The first gate portion is further divided into a lower region, an intermediate region, and an upper region, with the intermediate region having a maximum width greater than both the lower and upper regions.

Conclusion

Jooseong Yun's work in semiconductor technology showcases his innovative approach to device design. His patent application reflects a deep understanding of semiconductor structures and their functionalities. As he continues to develop his ideas, he may contribute significantly to advancements in the field.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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