Kyungki-do, South Korea

Jong-Cheol Kim

This inventor holds 1 USPTO granted patent. Top assignee: Citicorp USA, Inc.. Active years: 2002.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Jong-Cheol Kim. Retrieved from https://idiyas.com/inventor/jong-cheol-kim-m3uqoja5

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


% Patents Active = 100.0

Average Co-Inventor Count = 1.0

ph-index = 1


Company Filing History:


Years Active: 2002

Loading Chart...
1 patent (USPTO):Explore Patents

Title: Innovations by Jong-Cheol Kim

Introduction

Jong-Cheol Kim is a notable inventor based in Kyungki-do, South Korea. He has made significant contributions to the field of semiconductor device fabrication. His innovative work has led to the development of a unique test pattern that enhances the measurement of critical dimensions in wiring patterns.

Latest Patents

Jong-Cheol Kim holds a patent for a test pattern designed for measuring variations of critical dimensions of wiring patterns formed in the fabrication of semiconductor devices. This patent includes a test pattern comprising a first region as an active region of a semiconductor device and a second region as a device isolation region surrounding the first region. The design features a stepped layer with a different height from the first region, along with a plurality of parallel critical dimension bars across both regions. This configuration allows the test pattern to closely resemble the actual pattern on the chip region.

Career Highlights

Jong-Cheol Kim is currently associated with Citicorp USA, Inc., where he applies his expertise in semiconductor technology. His work focuses on improving the efficiency and accuracy of semiconductor device fabrication processes.

Collaborations

Due to space constraints, the collaborations section will be omitted.

Conclusion

Jong-Cheol Kim's innovative contributions to semiconductor technology, particularly through his patented test pattern, demonstrate his commitment to advancing the field. His work continues to influence the development of more efficient semiconductor devices.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
Loading…