San Marcos, CA, United States of America

John M Lower, Jr

This inventor holds 1 USPTO granted patent. Top assignee: Pacific Trinetics Corporation. Active years: 1999.

IDiyas Innovation Intelligence. (2026). Inventor Profile: John M Lower, Jr. Retrieved from https://idiyas.com/inventor/john-m-lower-jr

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


% Patents Active = 100.0

Average Co-Inventor Count = 3.0

ph-index = 1

Forward Citations = 31(Granted Patents)


Company Filing History:


Years Active: 1999

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1 patent (USPTO):Explore Patents

Title: Innovations of John M Lower, Jr.

Introduction

John M Lower, Jr. is an accomplished inventor based in San Marcos, CA (US). He has made significant contributions to the field of electrical components, particularly in the manufacturing of pre-terminated chips. His innovative approach has led to the development of a unique method and apparatus that enhances the efficiency of chip production.

Latest Patents

John M Lower, Jr. holds a patent for a "Method and apparatus for manufacturing pre-terminated chips." This invention involves a method for forming edge terminations in multi-layer electrical component chips, such as capacitor chips. The process includes cutting holes through a laminated printed circuit pad at specific locations that correspond to the boundaries between adjacent chips. These holes are filled with conductive ink to create plugs that span the boundaries. The pad is then cut along a grid of perpendicular lines, ensuring that the cut ink plugs form the appropriate edge terminations along each side edge of a chip. The cutting device is programmed to accurately cut holes over the desired edge termination sizes and positions.

Career Highlights

John M Lower, Jr. has been associated with Pacific Trinetics Corporation, where he has applied his expertise in electrical engineering and innovation. His work has contributed to advancements in the manufacturing processes of electrical components, showcasing his commitment to improving technology in this field.

Collaborations

Throughout his career, John has collaborated with notable colleagues, including Gordon O Zablotny and James W Horner. These partnerships have fostered a creative environment that encourages the exchange of ideas and the development of groundbreaking technologies.

Conclusion

John M Lower, Jr. is a prominent figure in the field of electrical engineering, with a focus on innovative manufacturing techniques for electrical components. His patent for the method and apparatus for manufacturing pre-terminated chips exemplifies his dedication to advancing technology. His contributions continue to influence the industry and inspire future innovations.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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