Pacific Trinetics Corporation

John M Lower, Jr

James W Horner

Gordon O Zablotny

A method and apparatus for forming edge terminations in multi-layer electrical component chips, such as capacitor chips, is arranged to cut holes through a laminated printed circuit pad at locations corresponding to the boundaries between adjacent chips when the pad is subsequently cut into individual chips. The holes are then filled with conductive ink to form plugs spanning the boundaries. The pad is then cut along a grid of perpendicular cutting lines defining the individual chip areas, simultaneously cutting through each of the ink plugs so that the cut ink plugs form the appropriate edge terminations along each side edge of a chip. The cutting device is suitably programmed to cut holes over the areas corresponding to the desired edge termination sizes and positions.

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San Marcos, CA, United States of America

John M Lower, Jr