Boise, ID, United States of America

John M Drynan

This inventor holds 25 USPTO granted patents, primarily in Semiconductor Technology. Top assignees: Micron Technology Incorporated, Other. Active years: 2003-2015.

IDiyas Innovation Intelligence. (2026). Inventor Profile: John M Drynan. Retrieved from https://idiyas.com/inventor/john-m-drynan

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


% Patents Active = 80.0

Average Co-Inventor Count = 1.7

ph-index = 10

Forward Citations = 286(Granted Patents)


Company Filing History:


Years Active: 2003-2015

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Areas of Expertise:
Interconnect Line
Wire Bonds
Dynamic Random Access Memory
Capacitor Structures
Semiconductor Constructions
Radiation-Imageable Material
Insulative Collars
Transistor Gate Line
Planarization
Conductive Contacts
Sacrificial Structure
TA2O5 Material
25 patents (USPTO):Explore Patents

Title: The Innovative Path of John M. Drynan: A Journey Through Patents and Technology

Introduction: John M. Drynan, based in Boise, ID, is a distinguished inventor with an impressive portfolio of 25 patents. His work primarily focuses on innovations in electrical interconnect technologies that enhance memory cell functionalities. This article explores his latest patents, career highlights, and notable collaborations.

Latest Patents: One of Drynan's latest inventions is a patent for an "Interconnect line selectively isolated from an underlying contact plug." This innovation provides a means for selectively electrically connecting an electrical interconnect line, such as a bit line of a memory cell, to an associated contact stud. Importantly, it isolates the interconnect line from other partially underlying contact studs for various electrical features, including capacitor bottom electrodes. This design enables the interconnect line to be partially connected to all contact studs, facilitating closer proximity of electrical features for higher integration levels. In subsequent fabrication steps, contact studs linked to non-interconnect line memory cell features can be efficiently isolated through the removal of a silicide cap, selective etching, and the creation of insulating sidewalls.

Career Highlights: John M. Drynan has made significant strides in his career, notably with his tenure at Micron Technology Incorporated, where he applied his expertise in semiconductor technologies and electrical engineering. His contributions have not only advanced the field but have also paved the way for more integrated and efficient memory systems.

Collaborations: Throughout his career, Drynan has collaborated with notable professionals in the field, including Fred D. Fishburn and Forest Chen. These collaborations have allowed for the sharing of ideas and expertise, enriching Drynan's innovative work and leading to significant advancements in technology.

Conclusion: John M. Drynan exemplifies the spirit of innovation with his substantial contributions to the technology sector, particularly in the realm of electrical interconnects and memory cells. With a robust patent portfolio and significant collaborations, he continues to influence the future of technology through his inventive spirit and dedication to advancements in the field.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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