Santa Clara, CA, United States of America

John J Nemec

This inventor holds 3 USPTO granted patents. Top assignees: Cypress Semiconductor Corporation, Multichip Technology. Active years: 1995-1998.


% Patents Active = 100.0

Average Co-Inventor Count = 2.0

ph-index = 3

Forward Citations = 151(Granted Patents)


Company Filing History:


Years Active: 1995-1998

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3 patents (USPTO):Explore Patents

Title: John J Nemec: Innovator in Memory Systems

Introduction

John J Nemec is a notable inventor based in Santa Clara, CA (US). He has made significant contributions to the field of memory systems, holding a total of 3 patents. His work focuses on enhancing the efficiency and functionality of memory systems through innovative designs and methods.

Latest Patents

One of his latest patents is a memory system and method for selecting a different number of data. This invention includes a main memory and a memory controller, where the main memory consists of at least one block with multiple banks. The memory controller features several data channels, each capable of accessing at least one bank in the main memory. Each data channel is equipped with a write first-in-first-out (FIFO) buffer, which supports cache purge operations and normal write operations efficiently. Additionally, it includes a reflective write FIFO buffer that facilitates coherent reads with simultaneous cache copyback operations. The memory controller intelligently selects the appropriate FIFO or FIFOs based on the type of data transaction and determines the suitable channel or channels according to the system bus size, data transaction size, and cache FIFO status. This memory system is designed to efficiently handle data transactions of varying lengths, from a byte to a long burst, and is adaptable to different bus and processor systems.

Another significant patent by Nemec is a dynamically configurable memory system featuring a programmable controller. This system includes a memory and a controller connected to the memory and a system bus. The controller is designed to receive a bus clock and control signals over the system bus, providing memory control signals with predetermined timing resolution. It incorporates a bus clock frequency multiplication circuit that generates an internal clock signal, which is crucial for producing memory control signals. The programmable timing register stores timing intervals for these signals, ensuring that the timing resolution remains nearly constant, regardless of the bus clock frequency. This innovative design enhances the overall performance and adaptability of memory systems.

Career Highlights

Throughout his career, John J Nemec has worked with prominent companies in the technology sector, including Cypress Semiconductor Corporation and Multichip Technology. His experience in these organizations has contributed to his expertise in memory systems and related technologies.

Collaborations

John has collaborated with various professionals in the field, including Donald A Lieberman, further enriching his work and contributions to memory system innovations.

Conclusion

John J Nemec is a distinguished

Profile summary based on public USPTO records.
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