Cypress Semiconductor Corporation

Multichip Technology

John J Nemec

Donald A Lieberman

A memory system includes a main memory and a memory controller, the main memory including at least one block which has a plurality of banks. The memory controller includes a plurality of data channels each of which can access at least one bank in the main memory. Each data channel comprises a write first-in-first-out (FIFO) buffer for efficiently supporting cache purge operations and normal write operations, and a reflective write FIFO buffer for efficiently supporting coherent read with simultaneous cache copyback operations. The memory controller selects the proper FIFO or FIFOs depending on the type of data transaction, and selects the proper channel or channels depending on the system bus size, the data transaction size, and the status of cache FIFO(s). The memory system can efficiently support data transactions having different data lengths or sizes from a byte to a long burst. The memory system can support different bus and processor systems and different data transactions in a highly efficient manner.

Memory system and method for selecting a different number of data

A memory system includes a memory and a controller coupled to the memory and a system bus. The controller is configured to receive a bus clock and control signals over the system bus and to provide memory control signals with a predetermined timing resolution to the memory. The controller includes a bus clock frequency multiplication circuit for generating an internal clock signal which is used to generate the memory control signals, and a programmable timing register for storing timing intervals of the memory control signals. The bus frequency multiplication circuit generates the internal clock signal by multiplying the frequency of the bus clock by a bus frequency multiplication factor which is selectively chosen to set the predetermined timing resolution for the memory control signals to a nearly constant value independent of the frequency of the bus clock. The bus frequency multiplication circuit may comprise a phase locked loop.

Dynamically configurable memory system having a programmable controller

A memory system includes a main memory and a memory controller. The main memory includes at least one block which has a plurality of banks. The memory controller includes a plurality of data channels each of which can access at least one bank in the main memory. Each data channel comprises a write first-in-first-out (FIFO) buffer for efficiently supporting cache purge operations and normal write operations, and a reflective write FIFO buffer for efficiently supporting coherent read with simultaneous cache copyback operations. The memory controller selects the proper FIFO or FIFOs depending on the type of data transaction, and selects the proper channel or channels depending on the system bus size, the data transaction size, and the status of the FIFO(s). The memory system can efficiently support data transactions having different data lengths or sizes from a byte to a long burst, and the timing resolution of the memory is enhanced regardless of the bus clock frequency. During burst transactions, the channels can run in an alternating fashion. During reads, the data is error-checked before being output to the system bus. The memory system can support different bus and processor systems and different data transactions in a highly efficient manner.

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Santa Clara, CA, United States of America

John J Nemec