Jiye Li

Title: Jiye Li: Semiconductor Patterning Innovation

Introduction

Jiye Li is an inventor associated with Singapore and Silicon Laboratories Inc. His patent work addresses a semiconductor manufacturing challenge: creating patterns with critical dimensions smaller than the minimum dimensions an available lithography tool can produce.

Latest Patents

The provided information lists one patent for Jiye Li: “Method for Reducing Critical Dimension of Patterns Generated Using a Lithography Tool.” The method first forms structures at the lithography tool’s minimum critical dimension, then reduces their dimensions using non-lithographic techniques.

For integrated-circuit manufacturing, the method forms a first hard mask by patterning a layer of a first material. It chemically modifies that mask to create a second hard mask, then patterns another layer of the first material to form a third hard mask and chemically modifies it to create a fourth. This sequence offers a way to produce finer semiconductor features than the lithography tool could form on its own. The supplied data attributes 1 patent to Li.

Career Highlights

The available information identifies Li’s association with Silicon Laboratories Inc. and highlights his work on semiconductor patterning. The patent describes a process that combines lithographic patterning with chemical modification to reduce feature dimensions.

Collaborations

The provided details do not identify specific co-inventors, research partners, or other collaborators for this patent.

Conclusion

Jiye Li’s listed patent presents a method for extending lithography capabilities through hard-mask processing and chemical modification, supporting the creation of smaller features in integrated-circuit manufacturing.