The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 07, 2026

Filed:

Jun. 22, 2023
Applicant:

Silicon Laboratories Inc., Austin, TX (US);

Inventor:

Jiye Li, Singapore, SG;

Assignee:

Silicon Laboratories Inc., Austin, TX (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10P 76/40 (2026.01); H10D 64/01 (2025.01); H10P 50/00 (2026.01);
U.S. Cl.
CPC ...
H10P 76/4085 (2026.01); H10D 64/01 (2025.01); H10P 50/71 (2026.01); H10P 50/73 (2026.01); H10P 76/405 (2026.01);
Abstract

A technique for forming semiconductor structures having a critical dimension (CD) smaller than the minimum lithographic CD capability of an available lithography tool used to form structures on a substrate forms structures having that minimum lithographic CD and reduces the CD of those structures using non-lithographic techniques. A method for manufacturing an integrated circuit includes forming a first hard mask on a substrate by patterning a first layer of a first material. The method includes forming a second hard mask of a second material on the substrate by chemically modifying the first hard mask. The method includes forming a third hard mask by patterning a second layer of the first material on the substrate. The method includes forming a fourth hard mask of the second material on the substrate by chemically modifying the third hard mask.


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