Jiunn Y Wu

Title: **Innovator Jiunn Y Wu: Advancing VLSI Circuit Technologies**

Introduction

Jiunn Y Wu is a distinguished inventor based in Dou-Lio, Taiwan. With an impressive portfolio of seven patents, he has made significant contributions to the field of Very-Large-Scale Integration (VLSI) circuits. His work focuses on enhancing circuit performance through innovative structures and materials.

Latest Patents

Among his notable inventions is the "Multi-level conduction structure for VLSI circuits." This patent addresses the formation of multi-level electrode metal structures and the interconnecting inter-level metal studs essential for VLSI fabrication. By etching away inter-level dielectric materials, this invention achieves an air dielectric between the levels, significantly reducing parasitic capacitance and improving circuit performance.

Another key patent is related to "LOCOS technology with reduced junction leakage." This invention involves a field oxide structure that minimizes defects through the formation of silicon nitride spacers and selective ion implantation. These advancements help confine stress-generated crystalline defects, leading to improved reliability in semiconductor devices.

Career Highlights

Jiunn Y Wu is currently employed at United Microelectronics Corporation, a leader in the semiconductor industry. His technical expertise has enabled him to drive forward multiple innovations that are vital for modern electronic applications.

Collaborations

Throughout his career, Wu has collaborated with talented coworkers like Water Lur and Anna Su. These partnerships have enhanced the development of groundbreaking technologies and fostered a collaborative research environment.

Conclusion

Jiunn Y Wu’s contributions to VLSI circuit innovation represent a remarkable journey of creativity and technical prowess. His patents not only push the boundaries of what is possible in semiconductor technology but also inspire future innovators in the field.