United Microelectronics Corp.

Jiunn Y Wu

Water Lur

Anna Su

Der Yuan Wu

Dey Y Wu

Shim F Tzou

This invention deals with the formation of the multi-level electrode metal structure and the interconnecting inter-level metal studs used in the fabrication of VLSI circuits. After the metal layers have been formed the inter-level dielectric material used in forming the structure is etched away leaving an air dielectric between the levels. The electrode metal and the inter-level metal studs are coated with a thin envelope oxide and the entire structure is covered with a passivation layer using material with a poor step coverage. The structure of this invention provides reduced parasitic capacitance, better step coverage in interconnecting layers, and improved circuit performance.

Multi-level conduction structure for VLSI circuits

A field oxide structure having a reduced number of defects is described. A field oxide mask is formed over a substrate having openings which expose portions of the substrate where the field oxide structures are to be formed. Silicon nitride spacers are formed on the sidewalls of the openings. Channel stop ions are selectively implanted through the opening into the substrate and then the thick field oxide structures are formed. Stress-generated crystalline defects are formed underlying the field oxidation regions at the edges of the openings. The silicon nitride spacers are removed. An additional source/drain ion implantation is performed by implanting ions to doped regions in the substrate deep enough into the substrate so that the crystalline defects are enclosed within the implanted regions to reduce junction leakage. The silicon dioxide, silicon nitride, and pad silicon oxide layers are removed to complete the field oxide structure.

Locos technology with reduced junction leakage

A new method of local oxidation using an additional source/drain implantation to protect the area from crystalline defects and thereby reduce junction leakage is achieved. A pad silicon oxide layer is provided over the surface of a silicon substrate. A silicon nitride layer followed by a silicon dioxide layer is deposited overlying the pad silicon oxide layer. Portions of the silicon dioxide, silicon nitride, and pad silicon oxide layers not covered by a mask are etched away to provide an opening to the silicon substrate where the field oxidation region is to be formed. Silicon nitride spacers are formed on the sidewalls of the opening. Channel-stop ions are selectively implanted through the opening into the substrate underneath the opening. The silicon substrate is oxidized within the opening to form the field oxidation region. Stress-generated crystalline defects are formed underlying the field oxidation region at the edges of the opening. The silicon nitride spacers are removed. An additional source/drain ion implantation is performed by implanting ions with energy high enough so that the ions form implanted regions deep enough into the silicon substrate so that the crystalline defects are enclosed within the implanted regions and wherein the enclosure of the crystalline defects within the implanted regions reduces junction leakage. The silicon dioxide, silicon nitride, and pad silicon oxide layers are removed completing the field oxidation of the integrated circuit.

LOCOS technology with reduced junction leakage

A new method of metal deposition in an integrated circuit is described. Semiconductor device structures are provided in and on a semiconductor substrate. At least one patterned conductive layer is provided for contacting the active elements of the device structures. The surface of the patterned conductive layer structure is irregular with horizontal and vertical components. An insulating layer is provided over the irregular structure patterned conductive layer. The insulator layer is covered with at least one spin-on-glass layer to fill the valleys of the irregular structure. The spin-on-glass layer is baked and cured, then covered with a second insulator layer. The spin-on-glass and two insulator layers are etched to provide openings to the patterned conductive layer wherein the etching is performed at low temperature so as to decrease the possibility of device degradation. The exposed spin-on-glass layer within the openings is degassed at a high temperature. A metal layer is sputtered over the surface of the substrate and filling the openings to the conductive layer and patterned to complete the metal deposition in the manufacture of integrated circuits.

Method for metal deposition without poison via

Multi-level conductor process in VLSI fabrication utilizing an air bridge

A first thin silicon oxide layer is formed the surface of a silicon substrate. A silicon nitride layer is deposited overlying said first thin silicon oxide layer. Portions of the silicon nitride layer and the first thin silicon oxide layer not covered by a mask pattern are etched through to the silicon substrate to provide a plurality of wide and narrow openings exposing portions of the silicon substrate that will form the device isolation regions. A layer of aluminum is deposited overlying the patterned nitride and first thin silicon oxide layers. A first layer of silicon oxide is deposited overlying the aluminum layer. The substrate is annealed whereby the aluminum layer reacts with the exposed portions of the silicon substrate within the openings to form an aluminum-silicon alloy wherein the alloy forms trenches into the surface of said substrate. The silicon oxide layer and the aluminum and aluminum-silicon alloy layers are removed leaving trenches in the substrate where device isolation regions are to be formed. A second thin layer of silicon oxide is grown over the surfaces of the nitride layer and conformally within the trenches. Channel-stops are selectively ion implanted through the openings into the substrate underneath the trenches. There are many methods to fill in the trenches such as photoresist etchback, BPSG reflow, chemical mechanical polishing, spin-on-glass planarization, etc., to complete the device isolation of the integrated circuit.

Local oxidation of silicon by using aluminum spiking technology

A first insulating layer is deposited over the surface of a silicon substrate. Those portions of the first insulating layers not covered by a mask pattern are etched through to the silicon substrate so as to provide a plurality of wide and narrow openings exposing portions of the silicon substrate that will form the device isolation regions. A second insulating layer is deposited overlying the patterned first insulating layer. A layer of an aluminum-silicon alloy is deposited overlying the second insulating layer. The aluminum-silicon layer is etched away whereby silicon nodules are formed on the surface of the second insulating layer. The second insulating layer is etched through to the first insulating layer where it exists and to the silicon substrate surface where the substrate is exposed within the wide and narrow openings. A first set of narrow trenches is etched into the exposed portions of the silicon substrate within the wide and narrow openings using the silicon nodules as a mask. A third insulating layer is deposited over the surface of the substrate and within the first set of trenches. The third insulating layer is etched back to leave spacers on the sidewalls of the first set of trenches which fill the trenches. A second set of trenches is etched into the silicon substrate not covered by a mask wherein the second set of trenches is immediately contiguous with the first set of trenches and wherein the first and second sets of trenches together correspond to the wide and narrow openings.

Growing community of inventors

Dou-Lio, Taiwan

Jiunn Y Wu