Cupertino, CA, United States of America

Jinfeng Liu

This inventor holds 3 USPTO granted patents. Top assignee: Synopsys, Inc.. Active years: 2012-2014.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Jinfeng Liu. Retrieved from https://idiyas.com/inventor/jinfeng-liu-fo4y2y9j

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


% Patents Active = 100.0

Average Co-Inventor Count = 3.0

ph-index = 2

Forward Citations = 103(Granted Patents)


Location History:

  • San Jose, CA (US) (2013)
  • Cupertino, CA (US) (2012 - 2014)

Company Filing History:


Years Active: 2012-2014

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3 patents (USPTO):Explore Patents

Title: Innovations of Jinfeng Liu in Static Timing Analysis

Introduction

Jinfeng Liu is an accomplished inventor based in Cupertino, CA, known for his contributions to the field of integrated circuit design. With a total of 3 patents, Liu has made significant advancements in static timing analysis (STA) methods that enhance the efficiency and accuracy of electronic designs.

Latest Patents

Liu's latest patents include innovative techniques for data compression and simultaneous multi-corner static timing analysis. The first patent, titled "Efficient data compression for vector-based static timing analysis," introduces a method for generating vectors from data sets related to integrated circuits. This method allows for the adjustment of vector data, applying incremental and differential compression techniques to optimize the storage and processing of timing analysis data. The second patent, "Simultaneous multi-corner static timing analysis using samples-based static timing infrastructure," outlines a method for performing STA across various process, temperature, and voltage conditions. This approach minimizes resource usage and accelerates the turnaround time for multi-corner analysis.

Career Highlights

Jinfeng Liu is currently employed at Synopsys, Inc., a leading company in electronic design automation. His work focuses on developing innovative solutions that streamline the design process for integrated circuits. Liu's expertise in static timing analysis has positioned him as a key contributor to advancements in the field.

Collaborations

Liu collaborates with notable colleagues, including Feroze P Taraporevala and Praveen Ghanta, who contribute to the innovative environment at Synopsys, Inc. Their combined efforts foster a culture of creativity and technical excellence.

Conclusion

Jinfeng Liu's contributions to static timing analysis through his patents reflect his commitment to innovation in integrated circuit design. His work continues to influence the industry, paving the way for more efficient electronic designs.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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