Kaohsiung, Taiwan

Jin Zhu Lee

This inventor holds 1 USPTO granted patent. Top assignee: Advanced Semiconductor Engineering, Inc.. Active years: 2004.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Jin Zhu Lee. Retrieved from https://idiyas.com/inventor/jin-zhu-lee

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

% Patents Active = 100.0

Average Co-Inventor Count = 4.0

ph-index = 1

Forward Citations = 8(Granted Patents)


Company Filing History:


Years Active: 2004

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1 patent (USPTO):Explore Patents

Title: Jin Zhu Lee and Integrated Circuit Package Testing.

Introduction

Jin Zhu Lee is an inventor associated with Kaohsiung, Taiwan, and Advanced Semiconductor Engineering, Inc. His patent work concerns testing integrated circuit packages.

Latest Patents

Lee is named on one patent, Test Assembly for Integrated Circuit Package. The invention describes a package substrate with contact pads connected in a daisy-chain pattern and a test board with its own daisy-chain-connected contact pads and test pads. The board’s contact pads are divided into groups, with each group connected to a pair of test pads and arranged in a line. The patent also describes a method for testing an integrated circuit package using the substrate and test board. Lee’s record includes 1 patent.

Career Highlights

Lee’s documented patent contribution focuses on an assembly and testing method for integrated circuit packages. The design organizes electrical contacts into groups to support package testing.

Collaborations

Lee’s listed coworkers include Po Jen Cheng and Heng Yu Kung. The available information identifies them as coworkers but does not specify their roles in the patent.

Conclusion

Jin Zhu Lee’s patent work addresses integrated circuit package testing through a structured arrangement of substrate and test-board contacts.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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