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Taipei Hsien, Taiwan

Jiing Lin

USPTO Granted Patents = 7

Average Co-Inventor Count = 1.4

ph-index = 2

Forward Citations = 25(Granted Patents)

Location History:

Hsin-Tien, TW (2005)
Taipei, TW (2004 - 2006)
Taipei Hsien, TW (2008 - 2011)

Company Filing History:

Via Technologies, Inc.

Years Active: 2004-2011

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7 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 8010775 - Method and related apparatus for reducing CHIPSET power consumption (2011-08-30),

2. 7469352 - Method and related apparatus for reducing chipset power consumption (2008-12-23),

3. 7404137 - Method and related apparatus for performing error checking-correcting (2008-07-22),

4. 7376886 - Method and related apparatus for data error checking (2008-05-20),

5. 7096291 - Method and device for arbitrating bus grant (2006-08-22),

6. 6967661 - Computer system which scans lines in tiled blocks of a display area (2005-11-22),

7. 6738956 - Circuit configuration of a chip with a graphic controller integrated and method for testing the same (2004-05-18),

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