Via Technologies, Inc.

Jiing Lin

Jie Ding

Iris Jiang

Chun-Yi Wu

Hsuan-Yi Wang

Kuang-Yu Tang

A method for reducing computer system power consumption. The computer system includes a memory module having a plurality of address pins, and a chipset having a plurality of driving units for driving the address pins. The method includes obtaining number of required address pins by detecting a capacity of the memory module, and disabling the driving units so as to make a number of the active driving units substantially equal to the number of the required address pins.

Method and related apparatus for reducing CHIPSET power consumption

A chipset has a plurality of driving units, each unit connecting to an address pin of a memory module for driving a one-bit address signal while accessing the memory module. The method detects configurations of memory modules, and determines which address pins are unused and makes corresponding driving units stop driving to reduce power consumption of unused address pins.

Method and related apparatus for reducing chipset power consumption

A method and related apparatus for performing error checking-correcting (ECC). The method divides a memory space provided by a memory into an ECC range and a non-ECC range. When data is read or written, the method determines the address of data is within the ECC range or the non-ECC range so as to decide whether error checking-correcting is performed on the data.

Method and related apparatus for performing error checking-correcting

A method for data error checking includes accessing a plurality of sets of data, each of the sets of data having a plurality of bits; integrating the plurality of sets of data into integral data; generating error checking data according to the integral data, the error checking data being changed following any change of the plurality of sets of data; dividing the error checking data into a plurality of sets of sub-checking data, each set of sub-checking data corresponding to one of the plurality of sets of data; and when transmitting each of the plurality of sets of data in order, transmitting the corresponding sub-checking data in the meantime.

Method and related apparatus for data error checking

A method for arbitrating a bus grant among a plurality of master devices for access to a shared bus is disclosed. The method includes the steps of starting to accumulatively count time in response to a data transfer request signal outputted by one of the master devices for requesting a data transfer, and re-estimating a bus-utility condition for the one of the master devices to access to the shared bus when a preset threshold value of time is counted up. In addition, an arbiter for a bus grant among a plurality of master devices for access to a shared bus is disclosed. The arbiter is characterized by including a plurality of timer devices in communication with the plurality of master devices, respectively.

Method and device for arbitrating bus grant

A computer system includes a monitor, a memory and a processing unit. The monitor includes a main area for displaying an image. The main area has a plurality of rows and a plurality of columns of tiles. Each tile has a plurality of rows and a plurality of columns of display units, and each display unit is for displaying a portion of the image according to corresponding pixel data. The memory includes a plurality of first sequential memory units and a plurality of second sequential memory units. The first sequential memory units are for storing pixel data of a first tile. The second sequential memory units are for storing pixel data of a second tile. The second tile is horizontally next to the first tile. The processing unit sequentially transmits pixel data of pixels in the first tile before transmitting pixel data of pixels in the second tile.

Computer system which scans lines in tiled blocks of a display area

The present invention generally relates to a circuit configuration of a chip and, more particularly to a circuit configuration of a chip with a graphic controller integrated and a method for testing such a circuit configuration, in which a test circuit is employed in a main control module such that a graphic controller is directly connected to a plurality of buses in a testing mode. Thus, the testing of the graphic controller is independent of the main controller module. Moreover, the testing requests are transmitted to the graphic controller by using frequency multiplying modes, and at least one multiplexer and at least one latch are used at the memory end, so that the required pin count for testing is lowered in the present invention.

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Taipei Hsien, Taiwan

Jiing Lin