Jianping Yan

Title: Innovations of Jianping Yan in Integrated Circuit Testing

Introduction

Jianping Yan is a notable inventor based in Milpitas, California, recognized for his contributions to the field of integrated circuit testing. With a total of three patents to his name, Yan has developed innovative methods that enhance the efficiency and effectiveness of testing integrated circuits.

Latest Patents

One of Jianping Yan's latest patents is titled "Method and apparatus for low-pin-count scan compression." This invention focuses on reducing test data volume and application time in scan-based integrated circuits. The method involves a programmable pipelined decompressor that decompresses a compressed scan pattern and drives the generated decompressed scan pattern to the scan data inputs of the integrated circuit. Another significant patent is the "Multiple-capture DFT system to reduce peak capture power during self-test or scan test." This method provides ordered capture clocks to detect faults within multiple clock domains, ensuring that all clock domains are not triggered simultaneously during a capture operation.

Career Highlights

Jianping Yan is currently employed at Syntest Technologies, Inc., where he continues to innovate in the field of integrated circuit testing. His work has significantly impacted the efficiency of testing processes, making them more reliable and less time-consuming.

Collaborations

Throughout his career, Yan has collaborated with esteemed colleagues, including Laung-Terng Wang and Zhigang Jiang. These collaborations have fostered a productive environment for innovation and development in integrated circuit technology.

Conclusion

Jianping Yan's contributions to integrated circuit testing through his innovative patents demonstrate his expertise and commitment to advancing technology in this field. His work continues to influence the efficiency of testing methods, making significant strides in the industry.