The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 24, 2012
Filed:
Jun. 29, 2011
Nur A. Touba, Austin, TX (US);
Laung-terng Wang, Sunnyvale, CA (US);
Zhigang Jiang, Burlingame, CA (US);
Shianling Wu, Princton Junction, NJ (US);
Jianping Yan, Milpitas, CA (US);
Nur A. Touba, Austin, TX (US);
Laung-Terng Wang, Sunnyvale, CA (US);
Zhigang Jiang, Burlingame, CA (US);
Shianling Wu, Princton Junction, NJ (US);
Jianping Yan, Milpitas, CA (US);
Syntest Technologies, Inc., Sunnyvale, CA (US);
Abstract
A low-pin-count scan compression method and apparatus for reducing test data volume and test application time in a scan-based integrated circuit. The scan-based integrated circuit contains one or more scan chains, each scan chain comprising one or more scan cells coupled in series. The method and apparatus includes a programmable pipelined decompressor comprising one or more shift registers, a combinational logic network, and an optional scan connector. The programmable pipelined decompressor decompresses a compressed scan pattern on its compressed scan inputs and drives the generated decompressed scan pattern at the output of the programmable pipelined decompressor to the scan data inputs of the scan-based integrated circuit. Any input constraints imposed by said combinational logic network are incorporated into an automatic test pattern generation (ATPG) program for generating the compressed scan pattern for one or more selected faults in one-step.