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For the Inventor, By the Inventor

San Jose, CA, United States of America

Jiann-Jeng Duh

This inventor holds 7 USPTO granted patents. Top assignee: Integrated Device Technology, Inc.. Active years: 2004-2007.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Jiann-Jeng Duh. Retrieved from https://idiyas.com/inventor/jiann-jeng-duh

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 7

% Patents Active = 85.7

Average Co-Inventor Count = 2.1

ph-index = 5

Forward Citations = 74(Granted Patents)


Company Filing History:

goldMedal7 out of 1,264 
 
Integrated Device Technology, Inc.
 patents

Years Active: 2004-2007

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7 patents (USPTO):Explore Patents
1. 7246300 - Sequential flow-control and FIFO memory devices having error detection and correction capability with diagnostic bit generation (2007-07-17),
2. 7209983 - Sequential flow-control and FIFO memory devices that are depth expandable in standard mode operation (2007-04-24),
3. 7158440 - FIFO memory devices having write and read control circuits that support x4N, x2N and xN data widths during DDR and SDR modes of operation (2007-01-02),
4. 7093047 - Integrated circuit memory devices having clock signal arbitration circuits therein and methods of performing clock signal arbitration (2006-08-15),
5. 7076610 - FIFO memory devices having multi-port cache memory arrays therein that support hidden EDC latency and bus matching and methods of operating same (2006-07-11),
6. 6795360 - Fifo memory devices that support all four combinations of DDR or SDR write modes with DDR or SDR read modes (2004-09-21),
7. 6778454 - FIFO memory devices that support all combinations of DDR and SDR read and write modes (2004-08-17),

Title: The Innovations of Jiann-Jeng Duh

Introduction

Jiann-Jeng Duh is a prominent inventor based in San Jose, California. He has made significant contributions to the field of memory devices, holding a total of seven patents. His work focuses on enhancing the functionality and reliability of FIFO (First In, First Out) memory devices.

Latest Patents

One of Jiann-Jeng Duh's latest patents is titled "Sequential flow-control and FIFO memory devices having error detection and correction capability with diagnostic bit generation." This invention includes FIFO memory devices that generate a data word along with a plurality of diagnostic bits. These diagnostic bits encode an error correction status of the data word and a path traversal status through the FIFO memory device. They identify whether the data word includes a corrected or uncorrected error, is without error, or is unchecked for errors.

Another notable patent is "Sequential flow-control and FIFO memory devices that are depth expandable in standard mode operation." This invention allows FIFO memory devices to support hybrid operating modes that enable depth expansion with other FIFO memory devices. The two hybrid modes include a write interface configured in standard mode and a read interface in first-word fall-through (FWFT) mode, as well as a second mode that reverses these configurations.

Career Highlights

Jiann-Jeng Duh works at Integrated Device Technology, Inc., where he continues to innovate in the field of memory technology. His expertise has led to advancements that improve the efficiency and reliability of memory devices used in various applications.

Collaborations

Throughout his career, Jiann-Jeng Duh has collaborated with notable colleagues, including Mario F Au and Tze-yuan Fang. These collaborations have contributed to the development of cutting-edge technologies in memory devices.

Conclusion

Jiann-Jeng Duh's contributions to the field of memory devices through his innovative patents have significantly impacted technology. His work continues to pave the way for advancements in error detection and memory functionality.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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