Integrated circuit memory devices having clock signal arbitration circuits therein and methods of performing clock signal arbitration

Abstract

A clock signal arbitration method includes arbitrating between first and second request signals generated in respective first and second clock domains that are asynchronously timed relative to each other, to obtain first arbitration results. These first arbitration results identify a relative queue priority between the first and second request signals. Additional steps are performed to transfer the first arbitration results into a third clock domain that is asynchronously timed relative to the first and second clock domains. The transfer operation may include arbitrating the first arbitration results in a third clock domain to obtain second arbitration results that confirm or correct the first arbitration results.