Jiann-Cherng James Lan

Title: Biography of Jiann-Cherng James Lan

Introduction

Jiann-Cherng James Lan is an accomplished inventor based in San Jose, California. He has made significant contributions to the field of semiconductor technology, particularly in low-power, high-speed logic circuits. With a total of nine patents to his name, Lan has established himself as a leading figure in innovative circuit design.

Latest Patents

One of his latest patents is titled "Single stage pulsed domino circuit for driving cascaded skewed static logic circuits." This invention involves a complementary metal oxide semiconductor (CMOS) low-power, high-speed logic circuit that consists of a cascaded chain of stages. The first stage is a pulsed domino logic circuit that receives data signals and a clocking pulse, conditioning it for evaluation during a brief window of time. The output connects to a series of skewed static logic gates, which alternate fast transitions for the information-carrying leading edge of input data signals. This design reduces power consumption while maintaining the speed of conventional domino logic circuits.

Another notable patent is the "Low power precharge scheme for memory bit lines." This invention introduces a low-power memory bit line precharge scheme that utilizes a first read precharge device and a second write precharge device. The second device is enabled only during a memory write operation, ensuring that the combined drive strength is sufficient to precharge the memory bit line effectively.

Career Highlights