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San Jose, CA, United States of America

Jianlin Wei

This inventor holds 2 USPTO granted patents. Top assignee: Cadence Design Systems, Inc.. Active years: 2004-2007.

USPTO Granted Patents = 2

% Patents Active = 50.0

Average Co-Inventor Count = 3.0

ph-index = 2

Forward Citations = 10(Granted Patents)

Company Filing History:

Cadence Design Systems, Inc.

Years Active: 2004-2007

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2 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 7177783 - Shape based noise characterization and analysis of LSI (2007-02-13),

2. 6826736 - Shape based noise tolerance characterization and analysis of LSI (2004-11-30),

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