New Taipei, Taiwan

Jian-Ping Wu

This inventor holds 1 USPTO granted patent and 1 published patent application. Top assignee: Nan Ya Technology Corporation. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Jian-Ping Wu. Retrieved from https://idiyas.com/inventor/jian-ping-wu-6plf57wi

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 1 

Average Co-Inventor Count = 1.0

ph-index = 1


Company Filing History:


Years Active: 2026

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1 patent (USPTO):Explore Patents

Title: Jian-Ping Wu: Semiconductor Device Inventor

Introduction

Jian-Ping Wu is an inventor based in New Taipei, Taiwan. His patent work addresses semiconductor device design and manufacturing, including the placement of testing modules within a scribe line.

Latest Patents

Wu is associated with 1 patent: “Semiconductor Device Having Testing Module Disposed Within Scribe Line and Method for Manufacturing the Same.” The invention describes a semiconductor device with two active regions separated by a scribe line. Each active region abuts a testing module positioned within the scribe line, and the modules are arranged in a direction substantially perpendicular to the line’s direction. The patent also covers a method for manufacturing the device.

Career Highlights

Wu’s documented patent contribution focuses on integrating testing modules into the scribe-line area between semiconductor active regions. This design places testing structures alongside the regions they serve while maintaining their specified arrangement.

Collaborations

Wu is associated with Nan Ya Technology Corporation, a company working in the semiconductor industry.

Conclusion

Jian-Ping Wu’s patent reflects a focused contribution to semiconductor testing and manufacturing, centered on arranging testing modules within the scribe line between active regions.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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