Hong Kong, China

Jia Chen

This inventor holds 1 USPTO granted patent and 1 published patent application. Top assignee: Ai Chip Center for Emerging Smart Systems Limited. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Jia Chen. Retrieved from https://idiyas.com/inventor/jia-chen-ig5jv1wd

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 1 

Average Co-Inventor Count = 1.0

ph-index = 1


Company Filing History:


Years Active: 2026

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1 patent (USPTO):Explore Patents

Title: Jia Chen - Innovator in Integrated Memory-Compute Circuit Design

Introduction

Jia Chen is an inventor based in Hong Kong, CN. He has made significant contributions to the field of integrated memory-compute circuit design. His innovative approach focuses on developing methods that enhance the efficiency and effectiveness of circuit layouts.

Latest Patent Applications

Jia Chen's notable patent application is titled "AUTOMATIC COMPILATION METHOD AND FRAMEWORK FOR GENERATING A LAYOUT OF INTEGRATED MEMORY-COMPUTE CIRCUIT." This application presents an automatic compilation method that includes constructing a design database with a basic design library and a collection of referencing architecture templates. The method involves receiving user specifications related to the integrated memory-compute circuit design, selecting a referencing architecture template, and parameterizing it according to the specifications. The process generates a physical layout based on the architecture using placement-and-routing algorithms. Additionally, it iterates a design exploration loop to optimize the layout and evaluates hardware metrics to determine the optimal physical layout.

Conclusion

Jia Chen's work in the field of integrated memory-compute circuit design showcases his innovative spirit and dedication to advancing technology. His contributions, particularly through his latest patent application, highlight the potential for improved circuit design methodologies.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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