San Francisco, CA, United States of America

Jerry R Burch

This inventor holds 2 USPTO granted patents. Top assignee: Cadence Design Systems, Inc.. Active years: 2001.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Jerry R Burch. Retrieved from https://idiyas.com/inventor/jerry-r-burch-fftorxh1

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


% Patents Active = 100.0

Average Co-Inventor Count = 2.0

ph-index = 2

Forward Citations = 29(Granted Patents)


Company Filing History:


Years Active: 2001

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2 patents (USPTO):Explore Patents

Title: Jerry R. Burch: Innovator in Combinational Verification

Introduction

Jerry R. Burch is a notable inventor based in San Francisco, CA, who has made significant contributions to the field of combinational verification. With a total of two patents to his name, Burch has developed innovative methods that enhance the efficiency and accuracy of circuit verification processes.

Latest Patents

Burch's latest patents include a "Method and system for combinational verification having tight integration of verification techniques." This invention integrates multiple verification methods to perform random simulation on the inputs of two combinational netlists. The process involves resolving cutpoint candidates to determine equivalence, utilizing BDD composition and SAT-based analysis as needed. The method ensures that if one approach fails, the information learned is passed to the other method, allowing for a comprehensive resolution of cutpoints.

Another significant patent is the "Method and system of latch mapping for combinational equivalence checking." This invention allows for the mapping of latches without depending on signal names or circuit structure. The refinement process iteratively compares mappings and applies random input vectors until the greatest fixed point of refinement is found. This method also addresses ternary latch mappings with "don't care" conditions, ensuring robust verification.

Career Highlights

Jerry R. Burch is currently employed at Cadence Design Systems, Inc., where he continues to innovate in the field of electronic design automation. His work focuses on improving verification techniques that are crucial for the development of reliable electronic circuits.

Collaborations

Burch collaborates with Vigyan Singhal, a fellow innovator in the field. Together, they contribute to advancements in verification methodologies that enhance the performance and reliability of electronic systems.

Conclusion

Jerry R. Burch's contributions to combinational verification through his innovative patents have significantly impacted the field of electronic design. His work at Cadence Design Systems, Inc. exemplifies the importance of continuous innovation in technology.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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