Taipei, Taiwan

Jen-Chih Hsiao

This inventor holds 1 USPTO granted patent. Top assignee: Taiwan Semiconductor Manufacturing Comp. Ltd.. Active years: 2005.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Jen-Chih Hsiao. Retrieved from https://idiyas.com/inventor/jen-chih-hsiao

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


Average Co-Inventor Count = 4.0

ph-index = 1

Forward Citations = 8(Granted Patents)


Company Filing History:


Years Active: 2005

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1 patent (USPTO):Explore Patents

Title: Innovations of Jen-Chih Hsiao in Semiconductor Testing

Introduction

Jen-Chih Hsiao is a notable inventor based in Taipei, Taiwan. He has made significant contributions to the field of semiconductor testing, particularly through his innovative patent that addresses dynamic lot dispatching in wafer and chip probing. His work is essential for improving efficiency in semiconductor manufacturing processes.

Latest Patents

One of Jen-Chih Hsiao's key patents is titled "Algorithms Tuning for Dynamic Lot Dispatching in Wafer and Chip Probing." This invention presents a method and system for flexible, comprehensive, on-line, real-time dynamic lot dispatching in a semiconductor test foundry. It is based on a two-phased, event-driven dispatching system structure. The patent features an adjustable priority formula and tuned algorithms integrated with PROMIS' constraint function, which provides a nearly optimum dispatching list on any tester at any time while reducing mistake operations. Exception rules are also included to manage special events, thereby improving daily dispatching manual effort. This invention can automatically dispatch engineering lots according to their testing capacity, resolve conflicts between wafer and package lots, efficiently reduce tester setup times, and replace daily manual dispatching sheets while maintaining a high CLIP rate in accordance with MPS.

Career Highlights

Jen-Chih Hsiao is currently employed at Taiwan Semiconductor Manufacturing Company Limited, a leading firm in the semiconductor industry. His role involves leveraging his expertise to enhance testing processes and improve operational efficiency. His contributions have been instrumental in advancing the company's capabilities in semiconductor manufacturing.

Collaborations

Throughout his career, Jen-Chih Hsiao has collaborated with notable colleagues, including Fu-Kang Lai and Ta-Chin Lin. These partnerships have fostered innovation and have been crucial in the development of advanced testing methodologies.

Conclusion

Jen-Chih Hsiao's innovative work in semiconductor testing exemplifies the importance of advancements in technology for improving manufacturing processes. His contributions continue to influence the industry positively.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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