Singapore, Singapore

Jeffrey Chee Wei-Lun

This inventor holds 1 USPTO granted patent. Top assignee: Chartered Semiconductor Manufacturing Ltd (Corporation). Active years: 2004.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Jeffrey Chee Wei-Lun. Retrieved from https://idiyas.com/inventor/jeffrey-chee-wei-lun

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

Average Co-Inventor Count = 4.0

ph-index = 1

Forward Citations = 28(Granted Patents)


Company Filing History:


Years Active: 2004

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1 patent (USPTO):Explore Patents

Title: Innovations by Jeffrey Chee Wei-Lun

Introduction

Jeffrey Chee Wei-Lun is a notable inventor based in Singapore, recognized for his contributions to semiconductor technology. He has developed innovative methods that enhance the performance of CMOS devices, showcasing his expertise in the field.

Latest Patents

One of his significant patents is titled "Dual Si-Ge polysilicon gate with different Ge concentrations for CMOS device optimization." This patent describes a method for forming dual Si-Ge poly-gates with varying Ge concentrations. The process involves creating an NMOS active area and a PMOS active area on a semiconductor substrate, separated by an isolation region. A gate oxide layer is grown over the substrate in each active area, followed by the deposition of a polycrystalline silicon-germanium (Si-Ge) layer with a specific Ge concentration. The NMOS area is blocked while the PMOS area is exposed, allowing for Ge plasma doping and laser annealing to achieve a higher Ge concentration in the PMOS area. This innovative approach results in dual Si-Ge polysilicon gates that optimize the performance of integrated circuit devices.

Career Highlights

Jeffrey is currently employed at Chartered Semiconductor Manufacturing Ltd, where he continues to push the boundaries of semiconductor technology. His work has significantly impacted the efficiency and effectiveness of CMOS devices, making him a valuable asset to the company.

Collaborations

Throughout his career, Jeffrey has collaborated with esteemed colleagues such as Chew-Hoe Ang and Wenhe Lin. These partnerships have fostered a creative environment that encourages innovation and the development of cutting-edge technologies.

Conclusion

Jeffrey Chee Wei-Lun's contributions to semiconductor technology, particularly through his patent on dual Si-Ge polysilicon gates, highlight his role as a leading inventor in the field. His work continues to influence the optimization of CMOS devices, showcasing the importance of innovation in technology.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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