This inventor holds 1 USPTO granted patent. Top assignee: Commissariat a L'energie Atomique Et Aux Energies Alternatives. Active years: 1990.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile
Company Filing History:
Years Active: 1990
Title: Innovations of Jean-Jacques Niez in Semiconductor Technology.
Introduction
Jean-Jacques Niez is a notable inventor based in Grenoble, France. He has made significant contributions to the field of semiconductor technology, particularly in the development of transistors. His innovative approach has led to the creation of a unique process for producing MIS transistors.
Latest Patents
Jean-Jacques Niez holds a patent for a process for the production of a MIS transistor with a raised substrate/gate dielectric interface wall. This process involves forming an electrically insulating layer on a semiconductor substrate, followed by the creation of a cavity with a rising wall. The method culminates in the formation of a transistor gate and the establishment of source and drain zones.
Career Highlights
Niez is associated with the Commissariat à l'Énergie Atomique et aux Énergies Alternatives, where he has been instrumental in advancing semiconductor technologies. His work has been recognized for its potential impact on the efficiency and performance of electronic devices.
Collaborations
Jean-Jacques Niez has collaborated with Pierre Jeuch, contributing to the development of innovative solutions in the semiconductor industry.
Conclusion
Jean-Jacques Niez's contributions to semiconductor technology exemplify the importance of innovation in advancing electronic components. His patented process for MIS transistors showcases his expertise and commitment to enhancing the field.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile