Bengaluru, India

Jaswinder Singh Sidhu

This inventor holds 1 USPTO granted patent. Top assignee: Mediatek Singapore Pte. Ltd.. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Jaswinder Singh Sidhu. Retrieved from https://idiyas.com/inventor/jaswinder-singh-sidhu

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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Company Filing History:


Years Active: 2026

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1 patent (USPTO):Explore Patents

Title: Jaswinder Singh Sidhu: Innovator in Memory Circuit Technology

Introduction

Jaswinder Singh Sidhu is a notable inventor based in Bengaluru, India. He has made significant contributions to the field of memory circuit technology. His innovative work has led to the development of a patent that enhances the efficiency of multi-bank memory systems.

Latest Patents

Jaswinder holds a patent for a "Low power read circuit for multi-bank memory." This invention includes a multi-bank memory structure that features a pair of far banks coupled to a first word line and a first pair of local bitlines. Additionally, it incorporates a pair of near banks connected to a second word line and a second pair of local bitlines. The design also includes a far global bit line linked to the first pair of local bitlines, a first NAND gate, and a near global bit line that outputs data through a global input/output (I/O) circuit.

Career Highlights

Jaswinder is currently employed at MediaTek Singapore Pte. Ltd., where he continues to innovate in the field of memory technology. His work has been instrumental in advancing the capabilities of memory circuits, making them more efficient and effective.

Collaborations

One of his notable coworkers is Manish Trivedi, with whom he collaborates on various projects within the company.

Conclusion

Jaswinder Singh Sidhu's contributions to memory circuit technology exemplify the impact of innovative thinking in the tech industry. His patent for a low power read circuit demonstrates his commitment to enhancing memory systems.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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