Suwon, South Korea

Jangseok Choi

This inventor holds 4 USPTO granted patents and 2 published patent applications and 2 EPO patents. Top assignee: Samsung Electronics Co., Ltd.. Active years: 2025-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Jangseok Choi. Retrieved from https://idiyas.com/inventor/jangseok-choi-jq0a7sto

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 4 

% Patents Active = 100.0

 

Average Co-Inventor Count = 4.3

ph-index = 1


Company Filing History:


Years Active: 2025-2026

Loading Chart...
Loading Chart...
4 patents (USPTO):Explore Patents

Title: Jangseok Choi: Innovator in Semiconductor Technology

Introduction

Jangseok Choi is a prominent inventor based in Suwon-si, South Korea. He has made significant contributions to the field of semiconductor technology, holding a total of 4 patents. His work focuses on enhancing the efficiency and functionality of semiconductor memory devices.

Latest Patents

One of Jangseok Choi's latest patents is for a semiconductor memory device and operation method thereof. This innovative device includes a cell array with multiple memory banks, a command decoder for processing read/write commands, and an address decoder for managing read and write addresses. The design allows for write data to be input via a write data pad in a single data rate method, facilitating efficient data transmission without deserialization processing. Additionally, the read data is transmitted directly from the input/output sense amplifier to the read data pad without serialization processing. In some embodiments, this semiconductor memory device is electrically and physically coupled to a central processing unit through hybrid copper bonding.

Another notable patent is for an apparatus and method for die-to-die (D2D) interconnects. This apparatus features a first die connected to a second die through a D2D interface. The first die includes an interconnect that provides lanes for communication with the second die, while the second die comprises multiple chiplet dies, each equipped with its own interconnect. This design optimizes the communication between connected chiplet dies and enhances overall performance.

Career Highlights

Jangseok Choi is currently employed at Samsung Electronics Co., Ltd., a leading company in the technology sector. His work at Samsung has allowed him to be at the forefront of semiconductor innovation, contributing to advancements that have a significant impact on the industry.

Collaborations

Throughout his career, Jangseok Choi has collaborated with notable colleagues, including Wangyong Im and Byoungkon Jo. These collaborations have fostered a creative environment that encourages the development of groundbreaking technologies.

Conclusion

Jangseok Choi's contributions to semiconductor technology through his patents and work at Samsung Electronics Co., Ltd. highlight his role as an influential inventor in the field. His innovative designs continue to shape the future of semiconductor devices and their applications.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
Loading…