Jan-An Hsieh

Title: The Innovative Mind of Jan-An Hsieh: A Patent for Circuit Design Verification

Introduction: Jan-An Hsieh, hailing from Hsinchu, Taiwan, is an accomplished inventor known for his contributions to the field of circuit design verification. With a focus on enhancing the reliability and accuracy of circuit designs, he holds a notable patent that reflects his innovative approach.

Latest Patents: Jan-An Hsieh's patent, titled "Method for verifying a circuit design by assigning numerical values to inputs of the circuit design," introduces a unique method for verifying circuit designs. This method involves assigning numerical values to the input ports of a circuit design based on a specific function. The function implemented is a=(a−1)+1, ensuring that the numerical values assigned are positive integers greater than or equal to 3, avoiding the values of 1 or 2. The method further details how to calculate the output value at the output port of the circuit based on the assigned numerical values, performed at a Boolean gate level.

Career Highlights: Jan-An Hsieh is associated with National Tsing Hua University, a prestigious institution known for its research and innovation in various scientific fields. His experience at the university has allowed him to engage deeply with advanced research in circuit design and verification methods.

Collaborations: Throughout his career, Jan-An Hsieh has collaborated with talented individuals such as Chun-Yao Wang and Shih-Chieh Wu. These collaborations have contributed to the successful development of innovative technologies and helped expand the knowledge base in circuit verification methodologies.

Conclusion: Jan-An Hsieh embodies the spirit of innovation in the realm of circuit design. His patent not only showcases his ingenuity but also paves the way for more reliable circuit designs. As he continues to work at National Tsing Hua University, he remains a significant figure in the landscape of technological advancements in Taiwan and beyond.