Palo Alto, CA, United States of America

Jagat B Patel

USPTO Granted Patents = 2 

Average Co-Inventor Count = 3.7

ph-index = 2

Forward Citations = 43(Granted Patents)


Company Filing History:


Years Active: 2003-2019

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2 patents (USPTO):Explore Patents

Title: Jagat B Patel: Innovator in Integrated Circuit Design

Introduction

Jagat B Patel is a notable inventor based in Palo Alto, CA, with a focus on optimizing integrated circuit (IC) design. He holds 2 patents that showcase his innovative contributions to the field of electronics and circuit design.

Latest Patents

His latest patents include "Placement-based congestion-aware logic restructuring," which describes systems and techniques for optimizing IC design. This patent outlines a process that transforms a circuit design into a logically-equivalent circuit design through several steps, including the creation of a Wire-Length-Area Model (WLAM) and the placement and routing of the second circuit design. Another significant patent is the "Method and system for automatically generating low level program commands as dependency graphs from high level physical design stages." This invention automates the generation of low-level design tool commands from high-level physical design stages, allowing for efficient execution of linked physical design processes.

Career Highlights

Jagat has worked with prominent companies in the industry, including Reshape, Inc. and Synopsys, Inc. His experience in these organizations has contributed to his expertise in integrated circuit design and optimization.

Collaborations

Throughout his career, Jagat has collaborated with notable professionals such as Margie Levine and Peter Dahl, enhancing his work through shared knowledge and expertise.

Conclusion

Jagat B Patel's contributions to integrated circuit design through his patents and professional collaborations highlight his role as an innovator in the field. His work continues to influence advancements in electronics and circuit optimization.

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