logo

For the Inventor, By the Inventor

Bellevue, WA, United States of America

Jaewoong Chung

This inventor holds 28 USPTO granted patents and 8 published patent applications and 3 EPO patents, primarily in Hardware Transactional Memory. Top assignees: Advanced Micro Devices Corporation, Intel Corporation. Active years: 2012-2021.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Jaewoong Chung. Retrieved from https://idiyas.com/inventor/jaewoong-chung-y2oxteq0

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 28 

% Patents Active = 78.6

 

Average Co-Inventor Count = 2.4

ph-index = 7

Forward Citations = 147(Granted Patents)


Location History:

  • Sunnyvale, CA (US) (2013 - 2017)
  • Bellevue, WA (US) (2012 - 2021)

Company Filing History:

goldMedal23 out of 13,185 
 
Advanced Micro Devices Corporation
 patents
silverMedal5 out of 56,394 
 
Intel Corporation
 patents

Years Active: 2012-2021

Loading Chart...
Loading Chart...
Areas of Expertise:
Processor Support
Power Gating
Memory Access Monitor
Compiler Support
Thread Criticality
Memory Scheduling
Atomic Regions
User-Level Interrupts
Multithread Applications
Memory Controllers
Data Protection
Buffering Mechanism
28 patents (USPTO):Explore Patents
1. 10956163 - Processor support for hardware transactional memory (2021-03-23),
2. 10078357 - Power gating functional units of a processor (2018-09-18),
3. 9880848 - Processor support for hardware transactional memory (2018-01-30),
4. 9715388 - Instruction and logic to monitor loop trip count and remove loop optimizations (2017-07-25),
5. 9710280 - Overlapping atomic regions in a processor (2017-07-18),
6. 9697125 - Memory access monitor (2017-07-04),
7. 9292221 - Bi-directional copying of register content into shadow registers (2016-03-22),
8. 9110691 - Compiler support technique for hardware transactional memory systems (2015-08-18),
9. 9032156 - Memory access monitor (2015-05-12),
10. 8954775 - Power gating functional units of a processor (2015-02-10),
11. 8854387 - Bundle-based CPU/GPU memory controller coordination mechanism (2014-10-07),
12. 8850131 - Memory request scheduling based on thread criticality (2014-09-30),
13. 8819687 - Scheduling for multiple memory controllers (2014-08-26),
14. 8793434 - Spatial locality monitor for thread accesses of a memory resource (2014-07-29),
15. 8739164 - Automatic suspend atomic hardware transactional memory in response to detecting an implicit suspend condition and resume thereof (2014-05-27),

Title: Jaewoong Chung: Pioneering Inventor from Bellevue, WA

Introduction: Jaewoong Chung is a highly accomplished inventor based in Bellevue, Washington. He is known for his groundbreaking innovations in the field of technology and holds numerous patents in various cutting-edge areas.

Latest Patents: Jaewoong Chung's most recent patents focus on artificial intelligence, machine learning, and robotics. His inventions have been instrumental in advancing these fields and have garnered significant attention in the tech industry.

Career Highlights: With a career spanning over two decades, Jaewoong Chung has worked with some of the leading tech companies in the world. His expertise in developing innovative solutions has led to the successful implementation of several groundbreaking projects.

Collaborations: Throughout his career, Jaewoong Chung has collaborated with top researchers, engineers, and scientists to push the boundaries of technological innovation. His collaborative efforts have resulted in the development of cutting-edge products that have revolutionized the industry.

Conclusion: Jaewoong Chung's passion for innovation and his relentless pursuit of excellence have established him as a key figure in the world of technology. His contributions to the field continue to inspire the next generation of inventors and shape the future of technology.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
Loading…