Suwon-si, South Korea

Jaesun Kim

This inventor holds 3 USPTO granted patents and 9 published patent applications. Top assignee: Samsung Electronics Ltd.. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Jaesun Kim. Retrieved from https://idiyas.com/inventor/jaesun-kim

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 3 

% Patents Active = 100.0

Average Co-Inventor Count = 3.6

ph-index = 1


Company Filing History:


Years Active: 2026

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3 patents (USPTO):Explore Patents

Title: Jaesun Kim: Semiconductor Package Inventor

Introduction

Jaesun Kim is an inventor based in Suwon-si, South Korea, and is associated with Samsung Electronics Ltd. His patent work focuses on semiconductor packaging and the design of electrical connections within a redistribution structure.

Latest Patents

Kim is named on 1 patent: “Semiconductor Package Including a Pad Comprising a Connection Portion Connecting a First and Second Pad Portions.” The invention describes a semiconductor package with a redistribution structure made of alternating redistribution and insulating layers. A semiconductor chip and bumps connect electrically to the redistribution layers. Each pad facing a bump has first and second pad portions offset in different directions, joined by a connection portion. A protruding feature in that connection portion defines recessed regions beside the two pad portions.

Career Highlights

The available information identifies Kim’s work on semiconductor packaging and his association with Samsung Electronics Ltd. The patent describes a pad configuration intended for use in the electrical connections of a semiconductor package.

Collaborations

Sanghyun Lee and Yeonho Jang are listed as Kim’s coworkers. The provided information does not specify whether they collaborated with him on this patent.

Conclusion

Jaesun Kim’s listed patent concerns a distinctive pad structure for semiconductor packaging, reflecting his documented work in this area.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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