Seoul, South Korea

Jae Wook Seo

This inventor holds 1 USPTO granted patent and 1 published patent application. Top assignee: Hynix Semiconductor Inc.. Active years: 2013.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Jae Wook Seo. Retrieved from https://idiyas.com/inventor/jae-wook-seo

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 1 

Average Co-Inventor Count = 4.0

ph-index = 1

Forward Citations = 3(Granted Patents)


Company Filing History:


Years Active: 2013

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1 patent (USPTO):Explore Patents

Title: Jae Wook Seo: Semiconductor Device Inventor

Introduction

Jae Wook Seo is an inventor associated with Seoul, South Korea, and Hynix Semiconductor Inc. His patent work addresses a structural challenge in manufacturing high-capacitance semiconductor capacitors: preventing storage nodes from leaning during fabrication.

Latest Patents

Seo is credited with 1 patent: “Semiconductor Device and Method for Manufacturing the Same, Which Prevents Leaning of a Storage Node When Forming a Capacitor Having a Plurality of Storage Nodes of ‘L’ or ‘+’ Shape Support Patterns.”

The invention describes cylinder-shaped storage nodes formed over a semiconductor substrate and support patterns that secure the nodes in an ‘L’ or ‘+’ arrangement when viewed from above. These supports help reduce stress on the storage nodes during the subsequent formation of dielectric and plate layers, helping prevent leaning and capacitor leakage.

Career Highlights

Seo’s listed patent reflects work on semiconductor device design and manufacturing. Its focus is improving the stability of capacitor storage nodes during fabrication.

Collaborations

The patent’s listed collaborators include Ho Jin Cho and Cheol Hwan Park. Seo’s company affiliation is Hynix Semiconductor Inc.

Conclusion

Jae Wook Seo’s patent addresses storage-node stability in semiconductor capacitors through support patterns designed to reduce leaning and support reliable device fabrication.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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