Suwon, South Korea

Jae Moo Choi

This inventor holds 4 USPTO granted patents and 2 published patent applications. Top assignee: Samsung Electronics Co., Ltd.. Active years: 2016-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Jae Moo Choi. Retrieved from https://idiyas.com/inventor/jae-moo-choi

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 4 

% Patents Active = 75.0

Average Co-Inventor Count = 4.3

ph-index = 1

Forward Citations = 2(Granted Patents)


Company Filing History:


Years Active: 2016-2026

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4 patents (USPTO):Explore Patents

Title: Jae Moo Choi: Semiconductor Circuit and Testing Innovations

Introduction

Jae Moo Choi is an inventor associated with Suwon, South Korea. His patent work includes innovations in semiconductor circuits and semiconductor package testing. Choi has 4 patents and has been associated with Samsung Electronics Co., Ltd.

Latest Patents

One of Choi’s latest patents, “Transmitting and Receiving Circuit Including a Calculation Amplifier and Test Device Including the Same,” describes a circuit designed to produce a reduced-level output signal. It includes a CMOS inverter, a calculation amplifier, and a resistor connected to a circuit node. The amplifier’s output and inverted input are connected, supporting the circuit’s signal-processing function.

Another patent, “Apparatus for Testing Semiconductor Packages,” describes a semiconductor integrated circuit test system that uses two testers. One tester conducts a test of a first characteristic within a relatively short test time. A second tester, coupled to the first, simultaneously tests a second characteristic across multiple semiconductor integrated circuits. The second test may take at least about two orders of magnitude longer than the first.

Career Highlights

Choi’s listed company affiliations include Samsung Electronics Co., Ltd. and Samsung Electronics Ltd. His patent portfolio reflects work on both circuit design and testing systems for semiconductor devices.

Collaborations

Choi’s listed coworkers include Ji Nyeong Yun and Jae Hong Kim. These associations connect his work to other contributors in the semiconductor field.

Conclusion

Jae Moo Choi’s patents address practical challenges in semiconductor signal processing and package testing, highlighting his contributions to technologies associated with Samsung Electronics.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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