Samsung Electronics Co., Ltd.

Jae Moo Choi

Jae Hong Kim

Ji Nyeong Yun

Jong Pill Park

Hyun Soo Jung

Jae Hee Han

Jae Hyun Baek

In Su Yang

A semiconductor integrated circuit test system can include a first semiconductor integrated circuit tester configured to conduct a first test of a first characteristic of one of a plurality of semiconductor integrated circuits, wherein the first test is completed by the first semiconductor integrated circuit tester within a first test time. A second semiconductor integrated circuit tester, can be coupled to the first semiconductor integrated circuit tester, where the second semiconductor integrated circuit tester can be configured to conduct a second test of a second characteristic of each of the plurality of the semiconductor integrated circuits simultaneously, wherein the second test is completed within a second test time that is at least about two orders of magnitude more than the first test time.

Apparatus for testing semiconductor packages

Systems for testing semiconductor packages

A memory test device for testing a memory device is provided. The memory test device includes a sequencer configured to output first and second sequencer outputs that are different from each other in response to a sequencer input. A first pattern generator is configured to output a first test pattern according to the first sequencer output. A second pattern generator is configured to output a second test pattern according to the second sequencer output. A selector is coupled to the first and second pattern generators and configured to output write data according to the first test pattern and the second test pattern.

Memory test device and operating method thereof

Growing community of inventors

Suwon-si, South Korea

Jae Moo Choi