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Clermont, FL, United States of America

J Ross Thomson

This inventor holds 15 USPTO granted patents. Top assignee: Agere Systems Inc.. Active years: 2003-2011.

IDiyas Innovation Intelligence. (2026). Inventor Profile: J Ross Thomson. Retrieved from https://idiyas.com/inventor/j-ross-thomson

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 15

% Patents Active = 60.0

Average Co-Inventor Count = 4.8

ph-index = 8

Forward Citations = 180(Granted Patents)


Company Filing History:

goldMedal15 out of 2,316 
 
Agere Systems Inc.
 patents

Years Active: 2003-2011

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15 patents (USPTO):Explore Patents
1. 7911006 - Structure and fabrication method for capacitors integratible with vertical replacement gate transistors (2011-03-22),
2. 7700432 - Method of fabricating a vertical transistor and capacitor (2010-04-20),
3. 7633118 - Structure and fabrication method for capacitors integratible with vertical replacement gate transistors (2009-12-15),
4. 7491610 - Fabrication method (2009-02-17),
5. 7259048 - Vertical replacement-gate silicon-on-insulator transistor (2007-08-21),
6. 7132297 - Multi-layer inductor formed in a semiconductor substrate and having a core of ferromagnetic material (2006-11-07),
7. 7078280 - Vertical replacement-gate silicon-on-insulator transistor (2006-07-18),
8. 7056783 - Multiple operating voltage vertical replacement-gate (VRG) transistor (2006-06-06),
9. 6906962 - Method for defining the initial state of static random access memory (2005-06-14),
10. 6828561 - Apparatus and method for detecting alpha particles (2004-12-07),
11. 6738294 - Electronic fingerprinting of semiconductor integrated circuits (2004-05-18),
12. 6709904 - Vertical replacement-gate silicon-on-insulator transistor (2004-03-23),
13. 6686604 - Multiple operating voltage vertical replacement-gate (VRG) transistor (2004-02-03),
14. 6667536 - Thin film multi-layer high Q transformer formed in a semiconductor substrate (2003-12-23),
15. 6639298 - Multi-layer inductor formed in a semiconductor substrate (2003-10-28),

Title: J Ross Thomson: Innovator in Integrated Circuit Technology

Introduction

J Ross Thomson is a prominent inventor based in Clermont, FL (US), known for his significant contributions to the field of integrated circuit technology. With a total of 15 patents to his name, Thomson has made remarkable advancements in the design and fabrication of semiconductor devices.

Latest Patents

Thomson's latest patents include a structure and fabrication method for capacitors that are integratable with vertical replacement gate transistors. This innovative process involves an architecture related to a vertical MOSFET device and a capacitor for use in integrated circuits. The integrated circuit structure features a semiconductor layer with a major surface, which includes a first doped region and additional regions of varying conductivity types. The design incorporates a capacitor with a bottom plate, dielectric layer, and a top capacitor plate. Another notable patent details a method of fabricating a vertical transistor and capacitor, further enhancing the capabilities of integrated circuits.

Career Highlights

Thomson has had a distinguished career at Agere Systems Inc., where he has played a crucial role in developing cutting-edge technologies. His work has significantly impacted the semiconductor industry, particularly in the area of integrated circuit design.

Collaborations

Thomson has collaborated with notable colleagues, including Paul Arthur Layman and Samir Chaudhry, contributing to various projects that advance semiconductor technology.

Conclusion

J Ross Thomson's innovative work in integrated circuit technology and his numerous patents underscore his importance in the field. His contributions continue to shape the future of semiconductor devices and integrated circuits.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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