The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 17, 2009
Filed:
Jun. 01, 2007
Samir Chaudhry, Irvine, CA (US);
Paul Arthur Layman, Ontario, CA;
John Russell Mcmacken, Summerfield, NC (US);
J. Ross Thomson, Clermont, FL (US);
Jack Qingsheng Zhao, Plano, TX (US);
Samir Chaudhry, Irvine, CA (US);
Paul Arthur Layman, Ontario, CA;
John Russell McMacken, Summerfield, NC (US);
J. Ross Thomson, Clermont, FL (US);
Jack Qingsheng Zhao, Plano, TX (US);
Agere Systems Inc., Allentown, PA (US);
Abstract
A process and an architecture related to a vertical MOSFET device and a capacitor for use in integrated circuits. The integrated circuit structure includes a semiconductor layer with a major surface and further including a first doped region formed in the surface. A second doped region of a different conductivity type than the first doped region is positioned over the first region. A third doped region of a different conductivity type than the second region is positioned over the second region. The integrated circuit includes a capacitor having a bottom plate, dielectric layer and a top plate. In an associated method of manufacture, a first device region. is formed on a semiconductor layer. A field-effect transistor gate region is formed over the first device region. A capacitor comprising top and bottom layers and a dielectric layer is formed on the semiconductor layer.