Milwaukie, OR, United States of America

Ismael Franco

This inventor holds 1 USPTO granted patent and 1 published patent application. Top assignee: Intel Corporation. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Ismael Franco. Retrieved from https://idiyas.com/inventor/ismael-franco

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 1 

Average Co-Inventor Count = 1.0

ph-index = 1


Company Filing History:


Years Active: 2026

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1 patent (USPTO):Explore Patents

Title: Ismael Franco and His Patent for Tunable Interconnects.

Introduction

Ismael Franco is an inventor associated with Intel Corporation in Milwaukie, Oregon. His patent work addresses electrical performance in fine-pitch socket interconnects.

Latest Patents

The provided information lists one patent for Franco: “Shielded Fine-Pitch High-Performance Impedance Tunable Interconnect.” The invention describes an apparatus and method for adjusting the differential impedance of pins in a socket or test system. Its pin assembly includes a pin block and fine-pitch differential pin pairs that make electrical contact with an electronic package. A volume between pins or adjacent pin pairs has a permittivity different from that of the pin-block material. Filling this volume with air or other materials can adjust the differential impedance by increasing or reducing it. Franco is credited with 1 patent.

Career Highlights

Franco’s listed patent reflects work on socket and test-system interconnects, where controlling impedance can support reliable electrical connections to electronic packages. The provided information identifies Intel Corporation as his company.

Collaborations

Daqiao Du and Brian Deford are identified as Franco’s coworkers. The available information does not specify their roles in the patent or whether they collaborated on it.

Conclusion

Ismael Franco’s listed invention focuses on tuning differential impedance in fine-pitch interconnects, contributing to the design of socket and test systems for electronic packages.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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