Portland, OR, United States of America

Ibrahim Hur

This inventor holds 16 USPTO granted patents and 3 published patent applications and 3 EPO patents. Top assignee: Intel Corporation. Active years: 2019-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Ibrahim Hur. Retrieved from https://idiyas.com/inventor/ibrahim-hur

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 16 

% Patents Active = 100.0

 

Average Co-Inventor Count = 4.1

ph-index = 1

Forward Citations = 4(Granted Patents)


Location History:

  • Hillsboro, OR (US) (2019 - 2020)
  • Portland, OR (US) (2020 - 2024)

Company Filing History:


Years Active: 2019-2026

Loading Chart...
Loading Chart...
16 patents (USPTO):Explore Patents

Title: Ibrahim Hur: Innovator in Code Prefetching and Cache Management

Introduction

Ibrahim Hur is a prominent inventor based in Portland, OR (US). He has made significant contributions to the field of computer architecture, particularly in the areas of code prefetching and cache management. With a total of 16 patents to his name, Hur continues to push the boundaries of technology.

Latest Patents

One of his latest patents is focused on code prefetch instruction. This invention describes embodiments of apparatuses, methods, and systems for code prefetching. In this embodiment, an apparatus includes an instruction decoder, load circuitry, and execution circuitry. The instruction decoder is designed to decode a code prefetch instruction, which specifies a first instruction to be prefetched. The load circuitry is responsible for prefetching the first instruction in response to the decoded code prefetch instruction. The execution circuitry executes the first instruction at a fetch stage of a pipeline.

Another notable patent by Hur involves delayed cache writeback instructions for improved data sharing in manycore processors. This invention describes methods and apparatus related to one or more delayed cache writeback instructions. In this embodiment, a delayed cache writeback instruction causes a cache block in a modified state in a Level 1 (L1) cache of a first core of a plurality of cores in a multi-core processor to transition to a Modified write back (M.wb) state. The M.wb state ensures that the cache block is written back to the Last Level Cache (LLC) upon eviction from the L1 cache.

Career Highlights

Ibrahim Hur is currently employed at Intel Corporation, where he applies his expertise in computer architecture to develop innovative solutions. His work has significantly impacted the efficiency and performance of multi-core processors.

Collaborations

Throughout his career, Hur has collaborated with notable colleagues, including Wim Heirman and Stijn Eyerman. These collaborations have fostered a creative environment that encourages the development of groundbreaking technologies.

Conclusion

Ibrahim Hur is a distinguished inventor whose work in code prefetching and cache management has advanced the field of computer architecture. His contributions continue to influence the design and functionality of modern processors.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
Loading…