Hyungcheol Shin

Title: Hyungcheol Shin’s Semiconductor Innovations.

Introduction

Hyungcheol Shin is an inventor associated with Gilbert, Arizona, and Motorola Corporation. His work focuses on silicon-on-insulator (SOI) semiconductor devices and fabrication methods. Shin is credited with 2 patents.

Latest Patents

“Reduced Stress Isolation for SOI Devices and a Method for Fabricating” describes a process for forming an isolation structure on an SOI substrate. It uses a three-layer stack consisting of an etchant barrier, a stress-relief layer, and an oxide mask. The method is designed to limit over-oxidation, preserve a planar substrate, and reduce oxidation-related dislocations. Its isolation structure has a small bird’s-head encroachment, which supports a higher edge threshold voltage and can improve source-to-drain leakage performance.

“Semiconductor-on-Insulator Device Having a Laterally-Graded Channel” describes an SOI device with laterally graded channel regions beneath a gate structure. Lightly doped regions extend through the semiconductor layer beneath the gate sidewalls, while the channel regions meet those lightly doped regions. The design places the source and drain in separate lightly doped regions.

Career Highlights

Shin’s listed patents address two aspects of SOI technology: isolation formation and channel design. Together, they describe approaches intended to manage device structure and electrical behavior in semiconductor fabrication.

Collaborations

Shin’s listed coworkers include Marco Racanelli and Heemyong Park. The provided information associates his work with Motorola Corporation.

Conclusion

Hyungcheol Shin’s two listed patents reflect contributions to SOI semiconductor fabrication, particularly isolation structures and laterally graded channels.