Motorola Corporation

Hyungcheol Shin

Marco Racanelli

Wen-Ling M Huang

Heemyong Park

A method for forming an isolation structure ( ) on a SOI substrate ( ) is provided. A three layer stack of an etchant barrier layer ( ), a stress relief layer ( ), and an oxide mask layer ( ) is formed on the SOI substrate ( ). The three layer stack is patterned and etched to expose portions of the etchant barrier layer ( ). The silicon layer ( ) below the exposed portions of the etchant barrier layer ( ) is oxidized to form the isolation structure ( ). The isolation structure ( ) comprises a bird's head region ( ) with a small encroachment which results in higher edge threshold voltage. The method requires minimum over-oxidation and provides for an isolation structure ( ) that leaves the SOI substrate ( ) planar. Minimal over-oxidation reduces the number of dislocations formed during the oxidation process and improves the source to drain leakage of the device.

Reduced stress isolation for SOI devices and a method for fabricating

A silicon-on-insulator semiconductor device (40) having laterally-graded channel regions (23A, 24A) and a method of making the silicon-on-insulator semiconductor device (40). The silicon-on-insulator semiconductor device (40) has a gate structure (16) having sidewalls (19, 21) on a semiconductor layer (12). Lightly doped regions (26A, 27A) extend through an entire thickness of a portion of the semiconductor layer (12) under the sidewalls (19, 21). A laterally-graded channel region (23A) is formed below the gate structure (16) and abutting one (26A) of the lightly doped regions. A source (33) is formed in a first (26A) of the lightly doped regions and a drain region (34) is formed in a second (27A) of the lightly doped regions.

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Gilbert, AZ, United States of America

Hyungcheol Shin