Namyangju, South Korea

Hyo Chul Yun

This inventor holds 1 USPTO granted patent. Top assignee: Mirae Corporation. Active years: 2009.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Hyo Chul Yun. Retrieved from https://idiyas.com/inventor/hyo-chul-yun-66i04u17

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

Average Co-Inventor Count = 3.0

ph-index = 1

Forward Citations = 2(Granted Patents)


Company Filing History:


Years Active: 2009

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1 patent (USPTO):Explore Patents

Title: Hyo Chul Yun: Innovator in Semiconductor Testing Technology

Introduction

Hyo Chul Yun is a notable inventor based in Namyangju, South Korea. He has made significant contributions to the field of semiconductor testing technology. His innovative approach has led to the development of a unique test tray and handler that enhances the efficiency of semiconductor chip testing.

Latest Patents

Hyo Chul Yun holds 1 patent for his invention titled "Test tray and handler using the test tray." This patent describes a semiconductor chip test handler that includes multiple chambers for heating, testing, and cooling packaged chips. The design allows for the horizontal and vertical movement of test trays, facilitating a streamlined testing process.

Career Highlights

Yun is currently employed at Mirae Corporation, where he continues to advance his work in semiconductor technology. His expertise in this area has positioned him as a valuable asset to his company and the industry at large.

Collaborations

Throughout his career, Hyo Chul Yun has collaborated with talented individuals such as Yong Sun Kim and Dae Gon Yun. These partnerships have contributed to the development of innovative solutions in semiconductor testing.

Conclusion

Hyo Chul Yun's contributions to semiconductor testing technology exemplify the impact of innovation in the field. His work continues to influence advancements in the industry, showcasing the importance of effective testing methods for semiconductor chips.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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